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Welcome to ATEEDA

The ultimate EDA tools for analog BIST IP

  • Cuts analog test cost
  • Test analog functions on digital testers
  • Simplifies testing of complex, crowded chips
  • Slashes test time for analog sections 
  • Enables in-life testing 
  • Available for ADCs & DACs

ATEEDA’s BIST suite of silicon-proven IP-generating tools provides dramatic reductions in the cost of analog test. Our philosophy is simple but extremely powerful, just like our tests: Exploit intelligence, not brute force. Our tools create simple tests with a small digital block and a tiny, robust analog IP.

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Tel: +44 (0)131 272 2754

Simplified Test Access

Chips are becoming so crowded they are nearly impossible to test, especially for System-on-Chip and System-in-Package products and at wafer probe.

BIST removes the need to provide test access for each analog block, saving pins and avoiding the need for complicated test multiplexers.

Read more about how BIST relieves test access problems

Reduced Test Costs

Analog Test Equipment is expensive, and has limited capacity for running tests simultaneously.

BIST allows analog System-on-Chip blocks to be tested in parallel on low-cost digital test equipment, resulting in up to 90% saving in test cost.

Read more about saving money with LinBIST

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