ATEEDA announces the successful implementation of a revolutionary time-efficient test method for e2v’s ASICs

18-Jun-2009

ATEEDA, a world leader in semiconductor test tools and solutions, has developed a new test regime for e2v’s sophisticated mixed signal automotive ASICs with ATEEDA’s OptimATE tool.

Following careful evaluation, extensive trials have confirmed that OptimATE can deliver a new level of analog test performance to e2v’s ASIC products; reducing overall test times whilst increasing the range and complexity of possible tests.

CEO, David Hamilton commented “Not only have we managed to improve the test coverage of analog circuitry components, we have also dramatically cut test duration. OptimATE tests are optimised to check individual specifications and additional circuit faults which are not necessarily reflected in a single test specification parameter. The smart work is done only once offline, so the test vectors themselves are very simple and really quick to load and execute.”

e2v has found that testing with the OptimATE tool is an order of magnitude quicker than the equivalent conventional test. Following successful results on substantial batches, further extensive data will be gathered in production alongside conventional tests, as e2v integrates testing with the OptimATE tool into full production.

e2v Mixed Signal ASIC General Manager, Andrew Beaumont commented: “Serving the automotive market, with its exacting requirements and quality demands, we need to maximise our high-end, low-frequency analogue IP test coverage. The OptimATE tool allows us to combine high performance testing with an overall reduction in test duration and is very adaptive to the specificities of our sensor acquisition chain IPs”.

ATEEDA has developed the concept of principally digital testing of analog hardware even further with a new tool, LinBIST. This gives built-in-self-test directly testing ADCs and DACs with minimal on-chip analog overhead.

The new tools will be launched during the world’s premier exhibition and conference event for the semiconductor design industry, DAC in San Francisco, July 2009. ATEEDA invites visitors to DAC booth 4102 in the IC Design Chain pavilion.