ATEEDA CEO David Hamilton joins top industry panel at VLSI Test Symposium 2010
24-Mar-2010
ATEEDA Chief Executive David Hamilton will be joining a panel of senior figures from the EDA and Semiconductor industries at the VLSI Test Symposium in April. The panel, which includes experts from Synopsys, Mentor Graphics, Virage Logic and Intel, will discuss the topic "EDA for Analog DFT/ATPG – Will SoC Pressure Make this a Reality?".
ATEEDA are leading the way with Built In Self Test solutions for this market, and CEO David Hamilton commented "Analog test makes up a significant proportion of the cost of SoC devices and takes significant time to develop. Solutions such as LinBIST from ATEEDA can significantly reduce this cost as well as test development time - our customers are telling us it's a win-win proposition". Delegates attending the panel can expect to join in a lively debate with this group of industry leaders.
The VLSI Test Symposium takes place from 19-21st April 2010 in Santa Cruz, California. The panel discussion "EDA for Analog DFT/ATPG – Will SoC Pressure Make this a Reality?" is Special Session 8C and will take place on Tuesday 20th April from 12:45-14:15.
