BIST IP Overview
The ultimate EDA tools for analog BIST
ATEEDA’s LinBIST and WaveBIST EDA tools and resultant silicon-proven IP provide dramatic reductions in the cost of analog test, and alleviate the test access problems in highly integrated devices.
Benefits:
- dramatic reductions in costs
- reduces pins needed for test in SoC and SiP (System-in-Package)
- slashes test time for analog sections
- tests analog blocks on digital testers
- allows parallel testing, even at wafer probe
- automates test program development
- offers in-life testing
Simple Configuration
We provide a simple GUI to generate IP to perfectly match your requirements.
Simply enter the convertor specifications that the test must check, select the interface options for integrating the result with your own design and output the solution.
With a single click, LinBIST or WaveBIST generates a mixed signal IP block ready to embed in your design. The IP consists of a tiny analog circuit and synthesisable HDL for a strictly limited number of digital gates. The test is implemented automatically without the designer writing a single line of code.
(WaveBIST uses an identical tool flow)
The process has been refined to fit your own established design, verification and test flow.
No Test Development
BIST does more than cut test costs; it cuts development time too because once your chip is verified, so is your test.
Characterisation
ATEEDA supplies automated characterisation software which communicates with the circuits on chip. It can use multiple test passes to quickly and accurately establish the detailed characteristics of individual devices on the lab bench.
LinBIST characterisation tool showing DNL and INL plots for an ADC
Choose ATEEDA to solve your analog test headaches and substantially reduce your test time and cost.